软件中转：TIM update -> TIM IRQ -> CPU/HAL callback -> ADC software start
硬件路由：TIM update -> TIM TRGO -> ADC trigger mux/edge -> ADC conversion

TIM2 到达更新条件
  -> 更新事件被 MMS 选择为 TIM2_TRGO
  -> ADC1 的触发选择指向 TIM2_TRGO
  -> ADC1 允许所需边沿
  -> ADC1 已使能且前一次转换允许接受新触发
  -> ADC 置位 STRT/EOC，数据进入 ADC_DR
  -> 可选 ADC IRQ 分发到 HAL 和应用回调

HCLK = 168 MHz
APB1 prescaler = /4 -> PCLK1 = 42 MHz
APB1 prescaler != 1 -> TIM2 kernel clock = 2 * PCLK1 = 84 MHz
PSC = 83 -> counter clock = 84 MHz / (83 + 1) = 1 MHz
ARR = 999 -> update/TRGO = 1 MHz / (999 + 1) = 1 kHz

APB2 prescaler = /2 -> PCLK2 = 84 MHz
ADC common prescaler = /4 -> ADCCLK = 21 MHz
12-bit, sample time = 84 cycles -> reference conversion budget
  = (84 + 12) / 21 MHz ~= 4.57 us
trigger period = 1 ms, greater than this single-conversion budget

事件生产者                 固定片内连接                事件消费者
TIM2 counter
  -> update event
  -> CR2.MMS selects update
  -> TIM2_TRGO ----------> ADC1 CR2.EXTSEL selects TIM2_TRGO
                            ADC1 CR2.EXTEN accepts rising edge
                            -> sample/convert -> EOC/OVR

HAL_Init
  -> SystemClock_Config_Reference
       -> HSI ready -> PLL ready -> SYSCLK switch
       -> AHB/APB prescalers and Flash latency
  -> board_adc_gpio_init          [板级待填]
  -> MX_TIM2_Init_Reference
       -> TIM2 clock gate/reset release
       -> PSC/ARR/counter mode
       -> master TRGO = update
  -> MX_ADC1_Init_Reference
       -> ADC1 clock gate/shared reset release
       -> ADC common prescaler, rank/channel/sample time
       -> external source = TIM2_TRGO, edge = rising
       -> ADC_IRQn configured for observation
  -> BSP_TriggerChain_Start
       -> HAL_ADC_Start_IT         [先武装接收端]
       -> HAL_TIM_Base_Start       [后启动源]

TIM2 counter reaches update condition
  -> update event / UIF
  -> TIM2_CR2.MMS exports update as TIM2_TRGO
  -> ADC1 trigger mux selected by EXTSEL sees TIM2_TRGO
  -> EXTEN rising-edge permission accepts event
  -> ADC1 samples selected board channel and converts
  -> ADC1_SR.EOC; result in ADC1_DR
  -> optional ADC_IRQn
  -> ADC_IRQHandler
  -> HAL_ADC_IRQHandler(&hadc1)
  -> HAL_ADC_ConvCpltCallback
  -> application later consumes diagnostic snapshot

HAL_TIM_Base_Stop(&htim2)
  -> 不再产生周期更新/TRGO
HAL_ADC_Stop_IT(&hadc1)
  -> 禁止 EOC/OVR interrupt，停止规则组接收

板级参考时钟：HSI 16 MHz（片内；实际项目可改，但必须重新计算）
  -> PLLM /16 = 1 MHz
  -> PLLN x336 = 336 MHz VCO
  -> PLLP /2 = 168 MHz SYSCLK
  -> AHB /1 = 168 MHz HCLK / Cortex-M4 core clock
       |
       +-> APB1 /4 = 42 MHz PCLK1
       |    -> APB1 prescaler != 1, TIM2 kernel clock = 84 MHz
       |    -> RCC_APB1ENR.TIM2EN gate
       |    -> optional RCC_APB1RSTR.TIM2RST pulse then release
       |    -> PSC /84 -> 1 MHz counter clock
       |    -> ARR /1000 -> 1 kHz update -> TIM2_TRGO
       |
       +-> APB2 /2 = 84 MHz PCLK2
            -> RCC_APB2ENR.ADC1EN gate
            -> optional shared RCC_APB2RSTR.ADCRST pulse then release
            -> ADC common prescaler /4 = 21 MHz ADCCLK
            -> sample 84 cycles + 12-bit conversion 12 cycles
            -> EOC/OVR -> optional ADC_IRQn

/* host_timer_trigger_test.c: Host Fake，只证明模型逻辑。 */
#include <assert.h>
#include <stdint.h>

typedef uint32_t fake_bool_t;
typedef uint32_t fake_status_t;

#define FAKE_FALSE UINT32_C(0)
#define FAKE_TRUE  UINT32_C(1)

#define FAKE_OK                    UINT32_C(0)
#define FAKE_ERR_TIMER_STOPPED     UINT32_C(1)
#define FAKE_ERR_TRGO_DISABLED     UINT32_C(2)
#define FAKE_ERR_TRGO_SELECTION    UINT32_C(3)
#define FAKE_ERR_ROUTE_DISCONNECTED UINT32_C(4)
#define FAKE_ERR_ROUTE_SOURCE      UINT32_C(5)
#define FAKE_ERR_ROUTE_SINK        UINT32_C(6)
#define FAKE_ERR_ADC_DISABLED      UINT32_C(7)
#define FAKE_ERR_ADC_SOURCE        UINT32_C(8)
#define FAKE_ERR_ADC_EDGE          UINT32_C(9)

#define FAKE_TRGO_NONE   UINT32_C(0)
#define FAKE_TRGO_UPDATE UINT32_C(1)

#define FAKE_EDGE_RISING  UINT32_C(1)
#define FAKE_EDGE_FALLING UINT32_C(2)

#define FAKE_SOURCE_TIMER2 UINT32_C(2)
#define FAKE_SINK_ADC1     UINT32_C(1)

typedef struct {
    fake_bool_t enabled;
    fake_bool_t trgo_enabled;
    uint32_t trgo_selection;
    uint32_t source_id;
    uint32_t update_events;
} fake_timer_t;

typedef struct {
    fake_bool_t connected;
    uint32_t source_id;
    uint32_t sink_id;
    uint32_t delivered_events;
} fake_route_t;

typedef struct {
    fake_bool_t enabled;
    uint32_t sink_id;
    uint32_t selected_source_id;
    uint32_t allowed_edges;
    uint32_t conversion_starts;
} fake_adc_t;

typedef struct {
    fake_timer_t timer;
    fake_route_t route;
    fake_adc_t adc;
    fake_status_t last_status;
} fake_fixture_t;

static fake_status_t fake_adc_trigger(fake_adc_t *adc,
                                      uint32_t source_id,
                                      uint32_t edge)
{
    if (adc->enabled == FAKE_FALSE) {
        return FAKE_ERR_ADC_DISABLED;
    }
    if (adc->selected_source_id != source_id) {
        return FAKE_ERR_ADC_SOURCE;
    }
    if ((adc->allowed_edges & edge) == UINT32_C(0)) {
        return FAKE_ERR_ADC_EDGE;
    }

    adc->conversion_starts++;
    return FAKE_OK;
}

static fake_status_t fake_route_deliver(fake_route_t *route,
                                        fake_adc_t *adc,
                                        uint32_t source_id,
                                        uint32_t edge)
{
    fake_status_t status;

    if (route->connected == FAKE_FALSE) {
        return FAKE_ERR_ROUTE_DISCONNECTED;
    }
    if (route->source_id != source_id) {
        return FAKE_ERR_ROUTE_SOURCE;
    }
    if (route->sink_id != adc->sink_id) {
        return FAKE_ERR_ROUTE_SINK;
    }

    status = fake_adc_trigger(adc, source_id, edge);
    if (status == FAKE_OK) {
        route->delivered_events++;
    }
    return status;
}

static fake_status_t fake_timer_tick(fake_fixture_t *fixture)
{
    if (fixture->timer.enabled == FAKE_FALSE) {
        fixture->last_status = FAKE_ERR_TIMER_STOPPED;
        return fixture->last_status;
    }

    fixture->timer.update_events++;

    if (fixture->timer.trgo_enabled == FAKE_FALSE) {
        fixture->last_status = FAKE_ERR_TRGO_DISABLED;
        return fixture->last_status;
    }
    if (fixture->timer.trgo_selection != FAKE_TRGO_UPDATE) {
        fixture->last_status = FAKE_ERR_TRGO_SELECTION;
        return fixture->last_status;
    }

    fixture->last_status = fake_route_deliver(&fixture->route,
                                              &fixture->adc,
                                              fixture->timer.source_id,
                                              FAKE_EDGE_RISING);
    return fixture->last_status;
}

static fake_fixture_t make_valid_fixture(void)
{
    fake_fixture_t fixture = {0};

    fixture.timer.enabled = FAKE_TRUE;
    fixture.timer.trgo_enabled = FAKE_TRUE;
    fixture.timer.trgo_selection = FAKE_TRGO_UPDATE;
    fixture.timer.source_id = FAKE_SOURCE_TIMER2;

    fixture.route.connected = FAKE_TRUE;
    fixture.route.source_id = FAKE_SOURCE_TIMER2;
    fixture.route.sink_id = FAKE_SINK_ADC1;

    fixture.adc.enabled = FAKE_TRUE;
    fixture.adc.sink_id = FAKE_SINK_ADC1;
    fixture.adc.selected_source_id = FAKE_SOURCE_TIMER2;
    fixture.adc.allowed_edges = FAKE_EDGE_RISING;
    return fixture;
}

static void test_valid_chain_delivers_once_per_tick(void)
{
    fake_fixture_t fixture = make_valid_fixture();

    assert(fake_timer_tick(&fixture) == FAKE_OK);
    assert(fake_timer_tick(&fixture) == FAKE_OK);
    assert(fixture.timer.update_events == UINT32_C(2));
    assert(fixture.route.delivered_events == UINT32_C(2));
    assert(fixture.adc.conversion_starts == UINT32_C(2));
}

static void test_source_stopped(void)
{
    fake_fixture_t fixture = make_valid_fixture();

    fixture.timer.enabled = FAKE_FALSE;
    assert(fake_timer_tick(&fixture) == FAKE_ERR_TIMER_STOPPED);
    assert(fixture.timer.update_events == UINT32_C(0));
    assert(fixture.adc.conversion_starts == UINT32_C(0));
}

static void test_trgo_disabled_or_wrong_selection(void)
{
    fake_fixture_t fixture = make_valid_fixture();

    fixture.timer.trgo_enabled = FAKE_FALSE;
    assert(fake_timer_tick(&fixture) == FAKE_ERR_TRGO_DISABLED);
    assert(fixture.adc.conversion_starts == UINT32_C(0));

    fixture = make_valid_fixture();
    fixture.timer.trgo_selection = FAKE_TRGO_NONE;
    assert(fake_timer_tick(&fixture) == FAKE_ERR_TRGO_SELECTION);
    assert(fixture.adc.conversion_starts == UINT32_C(0));
}

static void test_route_disconnected(void)
{
    fake_fixture_t fixture = make_valid_fixture();

    fixture.route.connected = FAKE_FALSE;
    assert(fake_timer_tick(&fixture) == FAKE_ERR_ROUTE_DISCONNECTED);
    assert(fixture.adc.conversion_starts == UINT32_C(0));
}

static void test_receiver_source_and_edge_rejection(void)
{
    fake_fixture_t fixture = make_valid_fixture();

    fixture.adc.selected_source_id = UINT32_C(99);
    assert(fake_timer_tick(&fixture) == FAKE_ERR_ADC_SOURCE);
    assert(fixture.adc.conversion_starts == UINT32_C(0));

    fixture = make_valid_fixture();
    fixture.adc.allowed_edges = FAKE_EDGE_FALLING;
    assert(fake_timer_tick(&fixture) == FAKE_ERR_ADC_EDGE);
    assert(fixture.adc.conversion_starts == UINT32_C(0));
}

static void test_receiver_disabled_after_one_event(void)
{
    fake_fixture_t fixture = make_valid_fixture();

    assert(fake_timer_tick(&fixture) == FAKE_OK);
    fixture.adc.enabled = FAKE_FALSE;
    assert(fake_timer_tick(&fixture) == FAKE_ERR_ADC_DISABLED);
    assert(fixture.timer.update_events == UINT32_C(2));
    assert(fixture.adc.conversion_starts == UINT32_C(1));
}

int main(void)
{
    test_valid_chain_delivers_once_per_tick();
    test_source_stopped();
    test_trgo_disabled_or_wrong_selection();
    test_route_disconnected();
    test_receiver_source_and_edge_rejection();
    test_receiver_disabled_after_one_event();
    return 0;
}

cc -std=c11 -Wall -Wextra -Werror -pedantic host_timer_trigger_test.c -o host_timer_trigger_test
./host_timer_trigger_test

/* bsp_timer_adc_trigger.h
 * 公开声明：不暴露 HAL 句柄，App 只依赖固定宽度类型和 BSP API。
 */
#ifndef BSP_TIMER_ADC_TRIGGER_H
#define BSP_TIMER_ADC_TRIGGER_H

#include <stdint.h>

typedef uint32_t bsp_trigger_status_t;

#define BSP_TRIGGER_OK              UINT32_C(0)
#define BSP_TRIGGER_ERR_CLOCK       UINT32_C(1)
#define BSP_TRIGGER_ERR_BOARD_GPIO  UINT32_C(2)
#define BSP_TRIGGER_ERR_TIM_INIT    UINT32_C(3)
#define BSP_TRIGGER_ERR_TIM_MASTER  UINT32_C(4)
#define BSP_TRIGGER_ERR_ADC_INIT    UINT32_C(5)
#define BSP_TRIGGER_ERR_ADC_CHANNEL UINT32_C(6)
#define BSP_TRIGGER_ERR_ADC_START   UINT32_C(7)
#define BSP_TRIGGER_ERR_TIM_START   UINT32_C(8)
#define BSP_TRIGGER_ERR_ADC_RUNTIME UINT32_C(9)

typedef struct {
    volatile uint32_t conversion_events;
    volatile uint32_t error_events;
    volatile uint32_t latest_sample;
    volatile uint32_t hal_adc_error;
    volatile uint32_t adc_sr_at_error;
    volatile bsp_trigger_status_t first_error;
} bsp_trigger_diag_t;

bsp_trigger_status_t BSP_TriggerChain_InitAndStart(uint32_t board_adc_channel);
void BSP_TriggerChain_Stop(void);
const bsp_trigger_diag_t *BSP_TriggerChain_GetDiag(void);

#endif

/* bsp_timer_adc_trigger.c
 * 参考实现，待目标工程编译和上板验证。
 */
#include "bsp_timer_adc_trigger.h"
#include "stm32f4xx_hal.h"

static TIM_HandleTypeDef htim2;
static ADC_HandleTypeDef hadc1;

static bsp_trigger_diag_t g_trigger_diag;

/* 板级层必须实现：配置实际 ADC channel 对应引脚为 analog/no-pull。 */
extern bsp_trigger_status_t board_adc_gpio_init(uint32_t board_adc_channel);

static void record_first_error(bsp_trigger_status_t error)
{
    if (g_trigger_diag.first_error == BSP_TRIGGER_OK) {
        g_trigger_diag.first_error = error;
    }
}

static bsp_trigger_status_t SystemClock_Config_Reference(void)
{
    RCC_OscInitTypeDef osc = {0};
    RCC_ClkInitTypeDef clk = {0};

    __HAL_RCC_PWR_CLK_ENABLE();
    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

    osc.OscillatorType = RCC_OSCILLATORTYPE_HSI;
    osc.HSIState = RCC_HSI_ON;
    osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
    osc.PLL.PLLState = RCC_PLL_ON;
    osc.PLL.PLLSource = RCC_PLLSOURCE_HSI;
    osc.PLL.PLLM = 16U;
    osc.PLL.PLLN = 336U;
    osc.PLL.PLLP = RCC_PLLP_DIV2;
    osc.PLL.PLLQ = 7U;
    if (HAL_RCC_OscConfig(&osc) != HAL_OK) {
        return BSP_TRIGGER_ERR_CLOCK;
    }

    clk.ClockType = RCC_CLOCKTYPE_SYSCLK |
                    RCC_CLOCKTYPE_HCLK |
                    RCC_CLOCKTYPE_PCLK1 |
                    RCC_CLOCKTYPE_PCLK2;
    clk.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
    clk.AHBCLKDivider = RCC_SYSCLK_DIV1;
    clk.APB1CLKDivider = RCC_HCLK_DIV4;
    clk.APB2CLKDivider = RCC_HCLK_DIV2;
    if (HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_5) != HAL_OK) {
        return BSP_TRIGGER_ERR_CLOCK;
    }
    return BSP_TRIGGER_OK;
}

void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
    if ((htim == NULL) || (htim->Instance != TIM2)) {
        return;
    }

    __HAL_RCC_TIM2_CLK_ENABLE();
    /* 仅限启动期且确认 TIM2 没有其他所有者。 */
    __HAL_RCC_TIM2_FORCE_RESET();
    __HAL_RCC_TIM2_RELEASE_RESET();
}

void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
{
    if ((hadc == NULL) || (hadc->Instance != ADC1)) {
        return;
    }

    __HAL_RCC_ADC1_CLK_ENABLE();
    /* ADCRST 是共享 ADC 复位；仅限所有 ADC 使用者静止的启动期。 */
    __HAL_RCC_ADC_FORCE_RESET();
    __HAL_RCC_ADC_RELEASE_RESET();

    /* 示例优先级，产品集成时按完整中断策略重选。 */
    HAL_NVIC_SetPriority(ADC_IRQn, 5U, 0U);
    HAL_NVIC_EnableIRQ(ADC_IRQn);
}

static bsp_trigger_status_t MX_TIM2_Init_Reference(void)
{
    TIM_MasterConfigTypeDef master = {0};

    htim2.Instance = TIM2;
    htim2.Init.Prescaler = 83U;
    htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
    htim2.Init.Period = 999U;
    htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
    htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
    if (HAL_TIM_Base_Init(&htim2) != HAL_OK) {
        return BSP_TRIGGER_ERR_TIM_INIT;
    }

    master.MasterOutputTrigger = TIM_TRGO_UPDATE;
    master.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
    if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &master) != HAL_OK) {
        return BSP_TRIGGER_ERR_TIM_MASTER;
    }
    return BSP_TRIGGER_OK;
}

static bsp_trigger_status_t MX_ADC1_Init_Reference(uint32_t board_adc_channel)
{
    ADC_ChannelConfTypeDef channel = {0};

    hadc1.Instance = ADC1;
    hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
    hadc1.Init.Resolution = ADC_RESOLUTION_12B;
    hadc1.Init.ScanConvMode = DISABLE;
    hadc1.Init.ContinuousConvMode = DISABLE;
    hadc1.Init.DiscontinuousConvMode = DISABLE;
    hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
    hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T2_TRGO;
    hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
    hadc1.Init.NbrOfConversion = 1U;
    hadc1.Init.DMAContinuousRequests = DISABLE;
    hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
    if (HAL_ADC_Init(&hadc1) != HAL_OK) {
        return BSP_TRIGGER_ERR_ADC_INIT;
    }

    channel.Channel = board_adc_channel;
    channel.Rank = 1U;
    channel.SamplingTime = ADC_SAMPLETIME_84CYCLES;
    channel.Offset = 0U;
    if (HAL_ADC_ConfigChannel(&hadc1, &channel) != HAL_OK) {
        return BSP_TRIGGER_ERR_ADC_CHANNEL;
    }
    return BSP_TRIGGER_OK;
}

static bsp_trigger_status_t BSP_TriggerChain_Start(void)
{
    /* 先武装接收端；外部触发模式下不会用 SWSTART 伪造事件。 */
    if (HAL_ADC_Start_IT(&hadc1) != HAL_OK) {
        g_trigger_diag.hal_adc_error = HAL_ADC_GetError(&hadc1);
        record_first_error(BSP_TRIGGER_ERR_ADC_START);
        return BSP_TRIGGER_ERR_ADC_START;
    }

    /* 后启动源。此处不启用 TIM2 update interrupt。 */
    if (HAL_TIM_Base_Start(&htim2) != HAL_OK) {
        (void)HAL_ADC_Stop_IT(&hadc1);
        record_first_error(BSP_TRIGGER_ERR_TIM_START);
        return BSP_TRIGGER_ERR_TIM_START;
    }
    return BSP_TRIGGER_OK;
}

void BSP_TriggerChain_Stop(void)
{
    /* 先停源，防止停止接收端时又到达新事件。 */
    (void)HAL_TIM_Base_Stop(&htim2);
    (void)HAL_ADC_Stop_IT(&hadc1);
}

bsp_trigger_status_t BSP_TriggerChain_InitAndStart(uint32_t board_adc_channel)
{
    bsp_trigger_status_t status;

    g_trigger_diag = (bsp_trigger_diag_t){0};

    status = SystemClock_Config_Reference();
    if (status != BSP_TRIGGER_OK) {
        record_first_error(status);
        return status;
    }

    status = board_adc_gpio_init(board_adc_channel);
    if (status != BSP_TRIGGER_OK) {
        record_first_error(BSP_TRIGGER_ERR_BOARD_GPIO);
        return BSP_TRIGGER_ERR_BOARD_GPIO;
    }

    status = MX_TIM2_Init_Reference();
    if (status != BSP_TRIGGER_OK) {
        record_first_error(status);
        return status;
    }

    status = MX_ADC1_Init_Reference(board_adc_channel);
    if (status != BSP_TRIGGER_OK) {
        record_first_error(status);
        return status;
    }

    return BSP_TriggerChain_Start();
}

void ADC_IRQHandler(void)
{
    HAL_ADC_IRQHandler(&hadc1);
}

void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
    if ((hadc != NULL) && (hadc->Instance == ADC1)) {
        g_trigger_diag.latest_sample = HAL_ADC_GetValue(hadc);
        g_trigger_diag.conversion_events++;
    }
}

void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
    if ((hadc != NULL) && (hadc->Instance == ADC1)) {
        g_trigger_diag.hal_adc_error = HAL_ADC_GetError(hadc);
        g_trigger_diag.adc_sr_at_error = hadc->Instance->SR;
        g_trigger_diag.error_events++;
        record_first_error(BSP_TRIGGER_ERR_ADC_RUNTIME);
    }
}

const bsp_trigger_diag_t *BSP_TriggerChain_GetDiag(void)
{
    return &g_trigger_diag;
}

/* main.c：App 使用层，参考实现，待目标工程编译。 */
#include "board.h"                  /* BOARD_ADC_CHANNEL 与板级 GPIO 实现 */
#include "bsp_timer_adc_trigger.h" /* 只依赖 BSP 公开声明 */

int main(void)
{
    HAL_Init();

    if (BSP_TriggerChain_InitAndStart(BOARD_ADC_CHANNEL) != BSP_TRIGGER_OK) {
        Error_Handler();
    }

    for (;;) {
        const bsp_trigger_diag_t *diag = BSP_TriggerChain_GetDiag();
        app_consume_trigger_snapshot(diag->conversion_events,
                                     diag->latest_sample,
                                     diag->error_events);
    }
}

TIM2_TRGO -> ADC conversion -> ADC DMA request
  -> DMA writes buffer -> HT/TC/error flag -> DMA IRQ
  -> HAL_DMA_IRQHandler -> ADC DMA callback -> application consumer

htim2.Init.Prescaler = 83U;
htim2.Init.Period = 999U;
master.MasterOutputTrigger = TIM_TRGO_UPDATE;

hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T2_TRGO;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;

/* 初始化和 channel 配置完成后： */
(void)HAL_ADC_Start_IT(&hadc1);  /* arm receiver */
(void)HAL_TIM_Base_Start(&htim2); /* start source */

CNT 不变
  -> 查 HSI/PLL/APB1、TIM2EN、TIM2RST 是否释放、CEN

CNT/UIF 正常，ADC 无 STRT/EOC
  -> 查 MMS=update
  -> 查 RM0090 路径确为 TIM2_TRGO
  -> 查 EXTSEL/EXTEN、ADON、初始化后是否又被覆盖

ADC EOC 出现，无 ADC_IRQHandler
  -> 查 EOCIE/OVRIE、NVIC enable/pending、向量表、优先级屏蔽

进入 ADC_IRQHandler，无应用回调
  -> 查是否调用 HAL_ADC_IRQHandler(&hadc1)
  -> 查句柄 Instance、HAL state、flag 与 interrupt enable

回调计数正常，样本不合理
  -> 触发链大概率已通；转查 channel/pin、analog mode、VDDA/VREF、输入范围、源阻抗和采样时间

出现 OVR
  -> 查触发是否快于转换/消费
  -> 查断点是否暂停 CPU 而 timer 继续
  -> 保存首个 SR/HAL error，再决定停止或恢复

TIM2 update
  -> TIM2_CR2.MMS exports TIM2_TRGO
  -> fixed F407 internal connection
  -> ADC1_CR2.EXTSEL/EXTEN selects source and edge
  -> ADC1 sample/convert
  -> EOC/OVR and optional IRQ callback